Project Requirements

Our project requirements were as follows:

  • Timing
    • MUST use 125 MHz / 8 ns clock
    • AND  process one data word per clock tick
    • (Note: a single data word consists of 4 samples)
  • Power
    • UNLIMITED (not really!)
    • The power used up by other components in VERITAS is much greater than any amount of power our FPGA could consume, but keeping power low will save resources in the long term
  • Area / Utilization
    • No hard limits (like with timing)
    • However, we can save a lot of resources by keeping our accelerator on the same FPGA as the current VERITAS logic installation
    • Ideally, we use less than 80% of logic (since routing typically becomes an issue at that point)
    • Currently 27% of resources are in use, so we want to use 53% or less

Performance Reports

Below are excepts from our utilization reports containing the relevant information needed to assess the performance of our design.

Timing Report

————————————————————————————————
| Timing Details
| ————–
————————————————————————————————

—————————————————————————————————
From Clock: clk
To Clock: clk

Setup  : 0 Failing Endpoints, Worst Slack 1.367ns, Total Violation 0.000ns
Hold    : 0 Failing Endpoints, Worst Slack 0.052ns, Total Violation 0.000ns
PW       : 0 Failing Endpoints, Worst Slack 3.500ns, Total Violation 0.000ns
—————————————————————————————————

Slack (MET) : 1.367ns (required time – arrival time)

Power Report

+———————————-+—————–+
| Total On-Chip Power (W)   | 0.156                |
| Design Power Budget (W) | Unspecified   |
| Power Budget Margin (W) | NA                      |
| Dynamic (W)                           | 0.065                |
| Device Static (W)                   | 0.091                |
| Effective TJA (C/W)               | 4.6                     |
| Max Ambient (C)                    | 84.3                  |
| Junction Temperature (C) | 25.7                  |
| Confidence Level                  | Low                  |
| Setting File                              | —                      |
| Simulation Activity File      | —                      |
| Design Nets Matched          | NA                     |
+———————————-+—————–+

Utilization Report

+————————-+——-+——–+————+——–+
|            Site Type         | Used | Fixed | Available | Util% |
+————————-+——-+——–+————+——–+

| Slice LUTs                   | 379    | 0          | 63400      | 0.60    |
|    LUT as Logic           | 379    | 0          | 63400      | 0.60    |
|    LUT as Memory     | 0         | 0          | 19000      | 0.00    |
| Slice Registers          | 332    | 0          | 126800    | 0.26    |
|    Register as FF         | 332   | 0          | 126800    | 0.26    |
|    Register as Latch  | 0        | 0           | 126800   | 0.00    |
+————————-+——-+——–+————+——–+

Analysis

  • Our timing requirements were satisfied
    • We used a 125 MHz / 8 ns clock
    • Worst slack is positive
  • Our power was satisfied
    • No power requirements
  • Our utilization was satisfied
    • The math here is complicated, but A3P250 (the installed VERITAS FPGA) has specific capacity:
      • 250,000 gates
      • 6,144 flip-flops (FFs)
    • We used 379 look-up tables (LUTs) and 332 FFs
      • LUTs usually require 100 gates or less to implement
      • Therefore, 37,900 gates are used
    • 332 / 6144 ≈ 5.4% FFs utilized
    • 37900 / 250000 ≈ 15% logic gates used
    • Overall, < 53% resources used!
  • Our project was successful!