To control our system, we designed a finite state machine which manipulates the datapath using control signals. It consists of 7 states with transitions controlled by counters for row and column. The state machine is described by the diagram below.
The signals above are assumed to be set to 0 if not listed. h and v are the column and row counter respectively. There is also a data_valid signal which tells the processing system when final data is ready. This signal is controlled by simple combinational logic regarding the counters.
As described in the datapath page, our design process was very modular. The complicated algorithm was split into simple modules implemented in VHDL. There are multiple ways to combine modules into a single design. One approach is to create a top.vhd file which manually instantiates each underlying module and lists every connection between them. This can quickly get out of hand. To make the process simpler, and to generate Xilinx IP products more easily, Vivado includes a block design creation tool. To connect our modules, we placed them in a block design and wired them together visually in combination with Xilinx IP such as FIFOs and Dividers. To test our design, we also implemented a Verilog testbench to run a simulation of our design.