The second objective to demonstrate MIMO converter potential was to design a power efficiency model that could be quickly applied to any arbitrary NxN MIMO converter. My approach to developing the general MIMO model was to first solve a simpler 2×2 MIMO converter problem, specifically the system presented in the simulation section. After finding a solution to the 2×2 MIMO model the plan was to scale the solution to NxN MIMO due to the fact no matter the system specifications any MIMO converter could be designed with capacitors in series and parallel configurations. Unfortunately, my derivations for the 2×2 model failed to closely align with the simulation results. Further discussion and recommendations for a model are presented in the next section tab, however I will describe my derivation process for documentation purposes and in the hope that it can still provide a basic framework in which to find a correct solution.
The theory behind the derivation process was to strike a balance between two previous methodologies presented in A Design Methodology for Switched-Capacitor DC-DC Converters by Michael Seeman and in An Insight into the Switching Process of Power MOSFETS: An Improved Analytical Losses Model. Seeman’s paper approaches solutions to 1×1 DC-DC Switched Capacitor(SC) converters by dividing the solution into two models: fast and slow switching limits, the final solution being an approximation between the two. Within these models charge transfers are either constant with losses dominated by switching behavior or switching loss negligible with loss majority attributed to charge transfers between capacitors. In contrast Rodriguezes demonstrates in his paper a methodology for deriving an analytic, flexible model for a buck converter by examining MOSFET switching behavior and applying Laplace transforms between time intervals. Importantly Rodriguez applies a new MOSFET model to characterize inductance affects in power loss. This model is shown below.
Rodriguezes Power MOSFET Model
The 2×2 MIMO circuit below is designed to meet the system specifications stated previously. Not shown in the picture is the gate driving connections to each MOSFET.
My derivation starts by trying to solve the situation where phase 2 is transitioning off while phase 1 is turning on. When this event occurs no current flows through the drain to source nodes of the MOSFETs theoretically, resulting in the topology shown below.
Only gate-source circuits need to be considered until the threshold voltage is reached. Further simplification results in the following circuits below
Circuits B(top) and C(bottom)
Finally, Laplace transforms are used to solve the above circuits, final solutions shown below.