In recent years, more and more researchers have started to develop accelerators for graph processing applications by utilizing Field Programmable Gate Array (FPGA) with benefits like fine-grained parallelism and energy efficiency. To demonstrate hardware’s performance for graph processing, designers need to run a benchmark suite for a standard evaluation and a meaningful comparison with prior works. Even though a variety of graph benchmark suites have already been developed, there is still no High-Level Synthesis(HLS) benchmark suite on the FPGA platform within our knowledge. To make contributions to HLS FPGA and graph processing communities, our capstone project can fulfill this gap and help to develop an HLS benchmark suite for graph algorithms implemented on FPGA-based platforms. We will mainly focus our efforts to develop four conventional graph apps such as Weakly connected components, ArticleRank, Betweenness Centrality, and Graph Coloring as well as its HLS kernel. The conventional graphs apps verify the correctness of its HLS kernel. The HLS kernels will first be accelerated in the CPU platform by using OpenMP to see the parallelism each kernel has. After that, each HLS kernel will be synthesized by Vivado HLS and its performance on the FPGA will be characterized by using three metrics like instruction mix, memory footprint, and synthesis result. Beyond that, each HLS kernel will also be optimized by using Vivado HLS pragmas and we will characterize their performance in terms of their execution time with different pragmas. Due to the reason that our capstone project is essentially a part of a large project from Dr. Silvia’s lab, we do not open-source our code right now. If you are interested, please contact Jian Gao through his email. 

Due to reconfigurability and good performance-power tradeoff, Field Programmable Gate Array (FPGA) is one of the most promising hardware platforms to execute these graph algorithms efficiently, in which graph algorithms are mapped to multiple computation units via hardware description languages (HDLs) or high-level synthesis (HLS) compilers. Since there are many different variants of graph algorithms written in HLS format with various characteristics, a lack of a standard for evaluations on FPGA platforms has hampered the progress of graph processing research, especially for HLS-based graph processing applications. In other words, a different implementation of graph algorithms can generate a higher variance than claimed performance improvement or decay. Therefore, a comprehensive HLS benchmark suite is needed to provide a uniform evaluation standard for meaningful comparison with prior works. Table below is a survey of the current tendency of graph benchmark suite and HLS benchmark suite.