An ‘European Option’ gives the holder the right, but not the obligation, to buy (call) or sell (put) a pre-specified security or commodity for a pre-specified price (Strike) at pre-specified date (Date of Maturity). In other words, when an individual purchases an Option, they have the ability to buy a stock, for example, at a pre-determined price, sometime in the future. Investors buy these financial products because it allows them to potentially make money on a stock price going up, without being exposed to the risk of the stock price falling. However, because the buyer of the Option has no downside risk, and can only make money, the seller has to charge an appropriate price. For European Options, the Black-Scholes model provides a simple closed-form analytical solution, that requires only inputs for the initial stock price, strike price, the risk-free rate, volatility, and the date of maturity.

Exotic Options

European Options are only exercise-able at the date of maturity and only dependent upon the stock price on that day. Some Options require knowledge of the path the stock took before reaching the final stock price. In this project, we consider a type of Exotic Option called a Barrier Option. The primary distinction between a European Option and a Barrier Option is that a Barrier Option can only be exercised if the stock price exceeded the Barrier price at some point during the life of the Option, this would be called a ‘Knock-In Call Option’. (Note: Knock-Out Options would imply the Option is voided if the Barrier is broken). Therefore, we can perform Monte Carlo simulations of the stock price until maturity to determine whether the Barrier was broken.

Example of Monte Carlo Simulations of a Barrier Option


Due to the intensive computing requirements of Monte Carlo simulations, our project utilizes the performance abilities of Field-Programmable Gate Array’s (FPGA) to expedite the calculations and outperform CPU’s. While we test the same Monte Carlo simulations in MATLab and C, we also implement in VHDL to simulate the speed up of the FPGA hardware.