VGA Driver VHDL Implementation

Core Principle

We developed a Video Graphics Array display driver in VHDL and tested it using a Nexys 4 DDR development board.  The driver operates on the standard 640 x 480 Raster Scanning principle, shown below.  The horizontal and vertical syncs (HS and VS) are generated using a horizontal (h) and vertical (v) counter that keep track of the current pixel.  Then the RGB values are changed for each pixel in range (640×480) creating the displayed image.  Additionally, even though this is a digital design, the VGA standard still requires that the screen be blacked out during the “retrace” time.

Character Based Display

Our VGA display driver has several features that work together to create the GUI.  First, there is functionality to display 7-bit ASCII characters to the screen using an ASCII character ROM.  By updating a message RAM, addressing into it using the current horizontal and vertical values, and then using the returned 7-bit ASCII value to address into the character ROM we can write, modify, and display any message or value.  This is how the right side display is implemented.

Plotting ADC Data

Basic Data Plotting

In order to plot our ADC values, we decided to use a 512 x 480 portion of the screen and have one vertical column correspond to a single sample point from the sample RAM.  This allows for the maximum image resolution while also making it easy to decimate the samples by factors of two.  The ADC values are plotted using the vertical and horizontal locations.  Since the top left pixel is defined as the origin we can use the current location in the scan to determine whether to plot or not.  In its simplest form, the driver takes the current horizontal position and uses it to address into the RAM.  If the ADC value that comes out matches the current vertical position, then the driver lights that pixel, displaying the ADC value.    However, since there can be gaps in the ADC values, two horizontally adjacent pixels might differ by more than one vertical pixel making the displayed plot have discontinuities. 

Plot Interpolation

We added a vertical interpolator to fill in the potential gaps between two values.  It operates on the same principle as described above but instead stores the ADC value directly preceding (h-1) the current horizontal position (h).  This additional piece of information makes it possible to do a different comparison where the FPGA knows the current ADC value and the previous one.  If the current vertical position is between those two values, it will light up all the pixels in that column until it leaves that range.  This generates a smoother plot with no discontinuities.

RGB Connector Circuit

The RGB values are set using a 9-bit resistor DAC, with 3-bits for each color.  This design is a modification of the RGB circuit on the Nexys 4 DDR development board.  The circuit is shown below.  We added C33 and R36 to help potentially denoise the outer shield of the RGB connector, but the signal was clean enough that we never had to add them to the board.