Our UI was simply a combination of the parts already described in the VGA driver section.  We implemented the interpolation program to plot the waveform, taking care to bias it to the correct pixel coordinate and truncate data of the screen.  Behind the waveform, we designed a simple set of axes with division markings to help users identify key factors of the signal. 

On the right hand side we used the character ROM and a message RAM to display and store the ASCII messages.  Because we only had about 20 lines that we could use for text, we limited the content to the user controls and basic measurements such as the maximum and minimum of the signal.  Our final design implemented:

  • The current time and voltage division settings
  • The desired time and voltage divisions when sampling a signal
  • The minimum and maximum voltages
  • A horizontal pan tracker

If we had more time we would have added more functionality, as laid out in the design specifications section.

User Controls

We added four 24 position rotary encoders and six push buttons to the board as our user controls.  The encoders were allocated to changing the voltage and time divisions as well as panning in time.  The buttons were used to set the resampling settings and tell the FPGA to begin resampling (i.e. wait to be triggered).

As previously described in the ADC section, we need to decimate the input when storing it into the RAM.  This meant that if the user wanted to look at a time division smaller (higher sample frequency) than the data currently in RAM, they would have to resample the data.  To communicate this to the user, whenever this occurs the text changes from the standard cyan color to magenta. 

Similarly, because our ADC is only 10 bits, and we have 9 bits of voltage resolution, we decided that allowing the user to scale the voltage didn’t make much sense to implement as  it would seriously degrade the graphical fidelity.  Therefore, anytime the user wants to change the voltage setting they must resample the wave.  A similar coloring scheme was devised to convey a difference between the current and desired voltage division settings.