Picking the ADC

Because of the VGA we didn’t need a particularly high resolution ADC.  However, we needed one with sufficiently high enough resolution to cover the entire range of our display.  Since our graphics display driver has a 640×480 resolution, we need at least 9 bits to have an ADC value that can represent each vertical pixel. 

Additionally, to get enough samples to make a 1 MHz wave look smooth on the screen we needed to sample at a much higher rate.  We chose to target our sample rate at 100 MHz for two reasons.   First, we already needed a 100 MHz clock for the FPGA, so it was convenient from both a parts perspective and a signal timing perspective to run both parts from the same clock generator.  Second, the Spartan 6 FPGA cannot be clocked much higher than 100 MHz.  This meant that if we tried to send data to it at a faster rate, it would effectively downsample the signal anyway.  Therefore, we were force to use a 100 MHz or less ADC with parallel data signaling.  

A quick search on Digikey told us that there were only two parts that met our specs, one of which was out of stock.  This essentially constrained us into using the AD9215, a 10-bit, 100 MHz, parallel data connection, SAR ADC.  After quickly looking through the datasheet we also discovered that it had a differentially signaled input, making it possible to directly wire the VGA to the ADC.  All together, this made the AD9215 the ideal part for our ADC.  

Mixed Signal Power Supply Considerations

After extensive conversations with Dr. Richard and Dr. Morley, as well as independent research, we learned that a common mixed signal design practice is to have either separate analog and digital power planes or a pi filter between the AVcc and DVcc pins of an ADC.  This is due to the noise generated on the analog supply by high-frequency digital switching. In its worst case it can cause an ADC, depending on its architecture and fabrication process, to latch up and potentially damage itself.  Additionally, it can also greatly reduce the SNR of the ADC and therefore the Effective Number of Bits (ENOBs) making our 10-bit converter significantly less accurate.

We elected to separate the analog and digital 3.3V power supplies by creating two separate power planes fed by two separate linear regulators.  Unfortunately, we were unable to make separate ground planes due to the number of layers on the final board.