The first constraint imposed by the FPGA is the limited amount of on-chip RAM. The Spartan 6 X9 package only has 589Kb of RAM. Therefore, if we wanted to store out 10-bit ADC values, we can only store about 50KSamples. Since it is convenient to have the number of samples be a power of two for decimation, we are limited to 32KS. Because of the low number of samples we can store, if we always tried to store samples with the same 100 MHz sample frequency, we would only ever get a small portion of lower frequency waves. Therefore, we have to downsample the wave before putting it into the RAM. We implemented this by allowing the user to set the time division they would like to look at, calculating the appropriate decimation factor, and the downsampling accordingly.
Likewise, because we only have 512 pixels on the screen we need to pick out those values from the RAM when displaying them. Therefore, we once again decimate the ADC values, now stored in RAM, based on the user’s chosen time division. Because the data is already stored in RAM the user does not need to resample the signal unless they exceed the sampling frequency of the data. Similarly, the 32KS in RAM and 512 display pixels allow for 7 different zoom settings, since we are decimating by powers of two.
We considered adding additional RAM to the design in order to overcome these problems. However, we quickly realized that in order to interface to the RAM we would need to be in a parallel interface since the address and data values would need to change every 100 MHz, just like the ADC. Considering the size of the RAM would be greater than 320Kb, this means that we would have at least 40KB of memory. If we round this to 64KB, we need at least 16 pins (assuming byte based addressing) just to address the device. Then an additional 10-15 for other data and control signals. Due to the already cramped space on the board and the limited number of usable FPGA pins, we decided to live with the amount of on-chip RAM we had.