FPGA Performance Optimization in High-Level Synthesis | FPGA Performance Optimization in High-Level Synthesis

Overview

We are working with Dr. Roger Chamberlain to apply HLS to FPGA data that will help on the preprocessing for the gamma-ray detection for Dr. Chamberlain’s Advanced Particle-astrophysics Telescope (APT) project. The goal for our project is to explore the development of data processing using the High-Level Synthesis (HLS), and to optimize the model to decrease the latency while controlling the tradeoffs of chip area. To complete the goal, we mainly focused on utilizing the first-in-first-out (FIFO) stream of data with appropriate pragma. We overwrite all the array data structure into the stream to enable dataflow and utilize vector data structure. After changing the data structure to a stream of samples, with each sample contained in a vector of 16 channels, the latency is now 7,719 cycles, which improved from Meagan Konst’s original implementation by 12 times. Future work on this project includes further optimizing current functions, along with adding other functions like centroiding, zero suppression, etc.